Analog-to-Digital conversion remains an essential function for the latest systems on a chip designed in nanometer process technologies. The performance of analog circuits is difficult to maintain with reduced supply voltage and increased device mismatch. Furthermore system designers wish to achieve low power consumption and small area designs that can be readily scaled between technologies. The successive approximation (SAR) ADC is suitable for implementation in nanometer process technologies as it does not contain circuit elements that may not be fabricated in digital process technologies and is readily scalable. In order to achieve small area, low power consumption and small capacitive load, capacitors must be sized as small as possible. The lower limit of capacitor size is set by thermal noise considerations, but mismatch between capacitors will limit achievable resolution before the thermal noise limit is reached. In order to allow use of very small capacitors, calibration must be introduced into the ADC.
The principle of operation of this type of ADC is shown for a simple 4 bit capacitor based ADC in FIG. 1. The SAR converter comprises of the input sample and hold, a comparator, logic block and a digital to analog converter which in this case is capacitor based. Initially the input voltage to be converted VIN, is sampled and held. The SAR logic connects the largest capacitor 8C to the reference voltage which changes the voltage at the negative terminal of the comparator by an amount directly proportional to the comparator size. This voltage is then compared against the held input voltage using the comparator. This result comprises the first MSB of the output digital word. Depending on the comparator decision the largest capacitor also is turned off (0) or remains on (1). The next largest capacitor 4C is then turned on and another comparison performed. In this manner the value of the VIN is approached iteratively at the negative terminal of the comparator and a digital word representing VIN is produced iteratively also.
The maximum achievable resolution of the SAR converter is dependent on the number of bits in the digital to analog converter. The practical limitation on the SAR resolution is dependent on the DAC i.e. the matching of the elements comprising the DAC. The purpose of the calibration schemes described in the prior art is to correct the elements of the DAC to improve the ADC resolution. There are numerous methods described in the art for calibrating SAR ADCs.
For example in a paper published by Liu, W.; Chiu, Y.; Background digital calibration of successive approximation ADC with adaptive equalisation Electronics Letters, Volume: 45, Issue: 9, 2009, Page(s): 456-458 a background Digital Calibration with adaptive equalisation is described. In this approach, as shown in FIG. 2 a slow-speed high-resolution reference ADC is placed in parallel with the SAR ADC that is to be calibrated. The reference ADC operates a factor M slower than the SAR ADC. The output of this ADC is therefore a very linear representation of the low frequency component of the input signal. The output of the SAR ADC is applied to a LMS adaptive filter. The output of this filter is controlled by the error between the decimated output of this filter and the output of the reference ADC. The effect of this feedback loop is to force the decimated output of the LMS filter to be equal to the reference ADC. Since the reference ADC output is linear the output of the LMS is also forced to be linear thereby producing a calibration. The problem with this approach is the requirement of a linear reference ADC and a large digital overhead.
In a paper published by He Yong; Wu Wuchen; Meng Hao; Zhou Zhonghua; A 14-bit successive-approximation AD converter with digital calibration algorithm ASIC, 2009. ASICON '09. IEEE 8th International Conference on 2009, Page(s): 234-237 a digital foreground calibration scheme is disclosed, as shown in FIG. 3. In this method the SAR algorithm itself is efficiently used for self-calibration. The capacitors representing the LSBs have a higher matching tolerance than the MSBs and may be sufficiently accurate to measure the relative error of the capacitors representing the MSBs. This approach stores the measured relative errors in a ROM and additional capacitors may be switched on in parallel with the MSBs in normal operating mode to provide a calibration. The disadvantage of this method is that it operates in foreground and required additional capacitors to effect calibration.
Another method is to use a Perturbation and Equalisation Approach, for example as disclosed in Wenbo Liu; Pingli Huang; Yun Chiu; A 12b 22.5/45MS/s 3.0 mW 0.059 mm2 CMOS SAR ADC achieving over 90 dB SFDR. Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, Page(s): 380-381. In this approach a pseudo-random (PN) perturbation is applied in series with the input signal, as shown in FIG. 4. The addition or subtraction of the perturbation is controlled by a pseudo-random sequence. A second sample is obtained with the perturbation reversed. This creates two input samples which utilise different paths through the ADC. Similar to the techniques used above an equalisation method is used to force the error between the paths to zero. This has again the effect of calibrating the ADC. This approach saves on area by using paths rather than a separate ADC. Disadvantages include the need to sample the input signal twice thus halving speed and secondly the reduction on input range of adding the PN signal.
Another method uses a calibration for gain error in split array, as disclosed in a paper by Yanfei Chen; Xiaolei Zhu; Tamura, H.; Kibune, M.; Tomita, Y.; Hamada, T.; Yoshioka, M.; Ishikawa, K.; Takayama, T.; Ogawa, J.; Tsukamoto, S.; Kuroda, T.; Split capacitor DAC mismatch calibration in successive approximation ADC. Custom Integrated Circuits Conference, 2009. CICC '09. IEEE Publication Year: 2009, Page(s): 279-282. In the case where attenuation capacitors are utilised to reduce the overall input capacitance of the SAR ADC, gain errors are introduced between the portions of the array on either side of the attenuation capacitor. These gain errors arise due to systematic and random sizing errors of the attenuation capacitor and also due to parasitic capacitance. In order to calibrate this error an additional capacitor is added to the array and it may be trimmed in order to adjust the effective gain of the attenuation capacitor to eliminate errors. This process is performed in the foreground. FIG. 5 details the capacitor array, showing the attenuation capacitor and a trim capacitor.
Problems with Calibrated SAR ADC converters include addition of extra analog hardware, inability to compensate for gain error, addition of high speed logic and large power overhead.
There is therefore a need to provide a calibration system and method specifically to enable high resolution SAR conversion on nanometer process technologies to overcome the above mentioned problems.